Semiconductor memory devices are continually being designed to be made smaller, faster, and to require less power such that they may be incorporated in portable devices that run on battery power. SRAM is volatile memory widely used in laptop computers and personal digital assistants (PDAs) in which each memory cell includes a transistor-based bi-stable latch that is either in an ‘on’ state or an ‘off’ state. SRAM devices may include a matrix of thousands of individual memory cells fabricated in an integrated circuit (IC) chip.
FIG. 1A illustrates one example of an eight transistor (8T) SRAM cell 100A. The 8T SRAM cell 100A includes a cross-coupled inverter 102A including PMOS transistors P1, P2 and NMOS transistors N1, N2. NMOS transistor N3 is coupled to a bit line (BL) and to node 104 of inverter 102A. The gate of NMOS transistor N3 is coupled to a write word line (WWL). NMOS transistor N4 is coupled to inverter 102A at node 106 and to a bit line bar (BLB). The gate of NMOS transistor N4 is coupled to WWL. Read port transistor N5, which functions as a read pull-down (RPD) transistor, has its gate coupled to node 106 of inverter 102A, its source coupled to ground, and its drain coupled to read port transistor N6, which functions as a read pass gate (RPG) transistor. The gate of read port transistor N6 is coupled to a read word line (RWL), and the drain of the RPG transistor N6 is coupled to the read bit line (RBL).
FIGS. 1B and 1C respectively illustrate a ten transistor (10T) SRAM cell 100B and a twelve transistor (12T) SRAM cell 100C. Each of 10T and 12T SRAM cells 100B and 100C include inverters 102B and 102C as well as read port cells 108B and 108C. Each of the read port cells 108B, 108C include an RPD transistor and an RPG transistor.
In each of the SRAM cells 100A, 100B, and 100C, the threshold voltage (Vth) of the RPG transistor is typically increased to minimize the subthreshold leakage current in order to reduce the overall power consumption of the SRAM array. The conventional method of increasing the Vth of the RPG transistor is by doping the channel of the RPG transistor. However, doping the channel of RPG transistor not only increases the number of processing steps for fabricating the SRAM, but it also results in an increase in the circuit footprint and the instability of the RPG transistor. For example, FIGS. 2A and 2B respectively illustrate cross-sectional and plan views of the RPG and RPD transistors in an SRAM cell, and FIGS. 2C and 2D respectively illustrate cross-sectional and plan views of the RPG and RPD transistors in an SRAM cell in which the Vth of the RPG transistor is higher than the Vth of the RPG transistor illustrated in FIGS. 2A and 2B. In order to isolate the channels of the RPG and RPD transistors, a shallow trench isolation (STI) structure is disposed between the drain of the RPD transistor and the source of the RPG transistor such that only the Vth of the RPG transistor is increased. The addition of the STI structure increases the floor plan of the SRAM cell.
In high-speed applications such as register files (RFs) and L1-caches, the Vth of a two read-port device is lowered in order to increase the operating speed of the devices. The reduced Vth increases the read-port current to reduce the access time, but this results in a significant increase in the leakage current. Consequently, a tradeoff is typically made between reducing the leakage current and increasing the speed of the transistors of the SRAM circuit.
Accordingly, an improved system and method for reducing the leakage current of transistors in high-speed applications is desirable.